In present semiconductor fabrication processes, semiconductor chips are frequently attached to other chips or other electronic structures. The attachment of a semiconductor chip is frequently accomplished by one of two techniques. The first technique is a wire bonding process in which each of a series of I/O bump terminals on a chip built on an aluminum bonding pad is sequentially bonded to the connecting pads on a substrate. The second technique is a flip chip attachment method in which all the I/O bumps on a semiconductor chip are first terminated with a solder material. A frequently used solder material is a lead/tin high melting temperature alloy. The semiconductor chip is then flipped over and the solder bumps are aligned and reflowed in a reflow furnace to effect all the I/O connections with the bonding pads on the substrate. One advantage achieved by the flip chip process is its applicability to very high density CMOS circuits and its high reliability in the interconnects formed when compared to the wire bonding process.
In the more recently developed interconnect technology of C4 (controlled collapse chip connection) which is a method of using a lead-rich lead/tin alloy to mount chips directly to high temperature ceramic substrates, C4 flip chip structures can be built directly over exposed aluminum vias located at the top surface of a wafer. The flip chip structure consists of a ball limiting metallurgy (BLM) and a solder ball/bump. The BLM used is a multi-layer structure such as Cr-Cu-Au which provides a conductive path between solder and the aluminum wiring exposed through vias in the wafer. The BLM structure also seals the vias and thus provides a restricted solderable area such that the wafer surface outside the BLM regions is protected by either a glass or a polymer film to limit the lateral flow of solder during subsequent reflow process. A column structure during chip interconnect can thus be assured.
A typical BLM structure is shown in FIG. 1 which is built on an electronic device 10. In the electronic device 10, a first dielectric layer 12 is deposited on a previously processed IC device and then a window 14 is opened by a photolithographic method and a metal such as tungsten is deposited to form a via or interconnect. After the metal layer is etched back, a second dielectric layer 18 is deposited on top of the first dielectric layer 12 and the metal via 14 by a blanket deposition method. A window 20 is then opened by a photolithographic method such that a conductive metal such as an aluminum-copper alloy can be deposited. After the conductive metal is etched back, layers of dielectric materials such as layer 22 of silicon oxide, layer 24 of silicon nitride and layer 26 of polyimide are sequentially deposited on top of the second dielectric layer 18 and the conductive metal plug 20. A window 28 is then etched away in the dielectric layers 22, 24 and 26 such that an adhesion layer of titanium tungsten 32 may be deposited. Other metallic layers such as those typically used in a ball limiting metallurgy (BLM) construction are then sequentially deposited. This is shown in FIG. 1 by layer 36 of a phased chromium-copper layer wherein a thin chromium layer of approximately 1,000 .ANG. is first evaporated as an adhesion layer and then a thicker layer of chromium-copper of approximately 2,000 .ANG. is deposited on top. A copper layer 38 of approximately 5 microns thickness is then deposited on top of the chromium-copper layer 36. It should be noted, even though not shown in FIG. 1, a very thin layer of gold (Au) is normally deposited on top of the copper layer for improved wettability. Thus, the four metallic layers that typically forms a BLM structure must use a resist to pattern a C4 structure and the photoresist layer must then be stripped and the copper, chromium-copper and titanium tungsten layers etched. A solder layer 42 is then deposited and formed by either an electroplating method or an evaporation method.
As shown in FIG. 1, the most widely used method of fabrication for a C4 structure is by a metal mask technology where both the BLM and the solder are evaporated through holes provided in a metal mask. Even though the same mask is used, the BLM and the solder are deposited in separate evaporators. The solder layer is normally deposited of about 100 micron thickness which requires a deposition time of approximately one hour. When a lead/tin solder is deposited, the lead/tin pool evaporates inhomogeneously due to the higher vapor pressure of lead. A subsequent reflow process is therefore required which is typically conducted in a hydrogen ambient atmosphere. One of the drawbacks of the evaporation process is that only 3% of the total evaporated solder reaches the BLM while the remainder is wasted on the mask and the evaporator walls. The metal masking and evaporation process therefore is not a very efficient solder building process.
An improved process from that of the metal mask/evaporation technique is the use of photolithography and electroplating for depositing solder. In this process, the initial BLM layers are first blanket applied by an evaporation or a sputtering process. A photoresist layer is then applied and patterned to expose the C4 regions of the BLM, which are then electroplated with about 100 microns of solder. The photoresist layer is then removed and the BLM regions is selectively etched using the plated solder bumps as a mask since the bumps are uneffected by the etching solutions. In this method, even though the photolithography which replaces the metal masking process can be operated more efficiently, the plating of the solder bumps is a rather complex process.
Others have used photolithographic process that consists of blanket depositions of BLM layers, photoresist application and patterning, BLM layers sub-etch, photoresist removal and solder deposition processes. The resulting BLM structure resembles that fabricated from a metal mask/evaporation technique and solder can be subsequently evaporated in a similar way. The evaporation of solder used in this process for building bumps decreases process throughput.
Still others have used electroless plating to fabricate BLM layers which is a maskless process that involves an activation of the exposed aluminum surface of the wafer vias for subsequent plating of the desired metallurgy, e.g., nickel-gold. The BLM structure fabricated by this process is compatible with solder evaporation process and not with the electroplating process.
In addition to the electroplating and evaporation techniques for depositing solder, solder dipping, solder ball placement, wire bonding and screening techniques have also been used to build solder bumps on a BLM structure. However, all the techniques involve a fully sequential process where the wafer is implicated from the first to the last step. Therefore, if at any point and specifically if towards the end of the processing steps an irrepairable defect occurs, the wafer and all the related cost incurred to that point would be lost.
Other related technologies include U.S. Pat. No. 5,219,117 which discloses a process for attaching solder balls to silicon wafers by using preformed solder balls which are deposited on the cavities of a silicon mold. The method utilizes preformed solder balls and not bulk solder and therefore requires additional processing steps for forming the solder balls. In another technology developed as disclosed in U.S. Pat. No. 5,388,327, a process for forming a film with holes punctured in it for using as a mold is disclosed. The holes are filled with a solder paste by a screening process and then the film is heated to melt the solder while the film is applied against a wafer and reflowed. Finally, the film is dissolved by a chemical solvent leaving the solder bumps on the wafer. The solder screening process and the process of dissolving the film with a solvent are both time consuming and contaminant producing.
An injection molded solder (IMS) process allows the controlled filling of cavities of a mold with molten solder or solder alloys of any composition. It is accomplished by using an IMS head where the solder is loaded and melted first and then placed tightly against a mold surface and glided across the surface. A vacuum channel is provided ahead of the solder slot such that the mold cavities are under vacuum. Molten solder then runs quickly into the cavities that are under vacuum and filling the cavities. After the cavities are filled and the mold is cooled and inspected, the IMS is ready for transfer to a mating surface on a substrate. In a copending application Docket No. YO893-0255 assigned to the common assignee of the present invention, the use of vacuum channels and vacuum links to force solder into cavities is disclosed. The copending application is hereby incorporated in its entirety by reference.
The IMS technology is also disclosed in U.S. Pat. No. 5,244,143, assigned to the common assignee of the present invention, which claims an IMS process based on the application of pressure for filling mold cavities in an IMS mold. The patent discloses that by the application of a positive pressure with a nitrogen gas, the filling of the micro-cavities in the mold can be facilitated.
It is therefore an object of the present invention to provide a method for building interconnect structures by injection molded solder that does not have the drawbacks and shortcomings of conventional fabrication technology.
It is another object of the present invention to provide a method for building interconnect structures by injection molded solder that does not require a time consuming deposition technique such as the forming of solder bumps by evaporation.
It is a further object of the present invention to provide a method for building interconnect structures by injection molded solder wherein a solder molding process and a BLM structure building process can be carried out concurrently.
It is another further object of the present invention to provide a method for building interconnect structures by injection molded solder wherein a unique mold structure is utilized.
It is still another object of the present invention to provide a method for building solder bumps on an electronic structure by injection molded solder wherein a substantially transparent mold is utilized to injection mold solder bumps of a predetermined shape.
It is yet another object of the present invention to provide a method for building solder bumps on an electronic structure by injection molded solder wherein a substantially transparent mold is used for the injection molding of solder bumps such that the bumps formed in the mold can be readily inspected after the molding process.
It is still another further object of the present invention to provide a method for building solder bumps on an electronic structure by injection molded solder wherein a substantially transparent mold is utilized to injection mold solder bumps and the coefficient of thermal expansion of the mold material matches substantially that of the electronic structure onto which the bumps are transferred.
It is yet another further object of the present invention to provide a method for building solder bumps on an electronic structure by injection molded solder wherein solder material is first injected into a mold under the assistance of a vacuum or a positive pressure.
It is still another further object of the present invention to provide a method for building solder bumps on an electronic structure by injection molded solder wherein the technology is suitable for use in the fabrication of large solder structures such as those required for ball grid arrays (BGA's) and column grid arrays (CGA's).